1. Filed of Invention
The present invention relates to electronic circuits, and more particularly the present invention relates to a semiconductor electrostatic discharge (ESD) protection circuits and a manufacturing method for the same
2. Description of Related Art
In the fabrication of an integrated circuit (IC), ESD is one of the main factors causing IC damage ESD is often seen in the work place. For example, when one walks on a carpet with semiconductor wafers, if relative humidity (RH) is high, an electrostatic voltage of about few hundred volts may exist on one""s body and wafers. If the RH is very low, the electrostatic voltage may be even as high as about few thousand volts. If a conductive object occasionally contacts the wafers, a strong ESD could occur and damage the ICs on the wafers. ESD is especially a serious problem during fabrication of a complementary metal oxide semiconductor (CMOS) device
In order to protect wafers from ESD damage, many methods to solve the ESD problems have been proposed. The most common conventional method is to make an ESD protection circuit between input/output (I/O) pads on a chip and internal circuits, is designed to begin conducting or to undergo breakdown, thereby providing an electrical path to ground. Since the breakdown mechanism is designed to be nondestructive, the circuits provide a normally open path that closes only when a high voltage appears at the input or output terminals, harmlessly discharging the node to which it is connected. Recently, the spike discharge ESD protection structure is under investigation,
In above descriptions, the spike ESD phenomenon occurs around the spike tips on a conductive object because the electric field on the spike is much stronger even though the electrostatic surface charges on the spike tips, where the accumulated electrostatic surface charges are more easily triggered for discharging
As the device feature size reduces from sub-micron or even down to deep-submicron ranges, miniaturizing of the feature sizes is desired to reduce the surface area coverage of silicon in order to effectively increase the integration of ICs. Conventional ESD protection devices usually connected between I/O pads and the internal circuits, occupy some surface area on the wafer therefore the integration of ICs is limited. For example, a typical ESD protection circuit device (NPN transistor) having an ESD threshold of about 3.6-3.9 KV for sub-micron CMOS processes, occupies approximately 15 xe2x96xa1mxc3x97116 xe2x96xa1 m (1,740 xe2x96xa1m2 of silicon area). Ideally, it would be highly desirable to design an ESD protection circuit device that does not occupy any extra surface area on the wafer, thereby substantially increasing the integration of ICs
FIG. 1 is a schematic diagram illustrating a conventional ESD protection circuit. Referring to FIG. 1, the ESD current input through the pad 150 is discharged by through a PMOS transistor 170 that leads to a ground Vss so that the internal circuit 180 is protected. Since the NMOS transistor 160 and PMOS transistor 170 of the conventional ESD protection circuit device are located outside the pad, it consumes more available surface of wafer
As embodied and broadly described herein, the invention is directed towards providing an ESD protection circuit device located under the pad of semiconductor devices and a method for fabricating the same that meets the challenges of reduced spatial availability thereby effectively increasing the integration of ICs. The present invention provides an ESD protection circuit device that does not occupy any extra surface area on the wafer thereby substantially increasing the integration of ICs
According to the preferred embodiment, the present invention provides a structure in ESD protection circuit device and a method of fabricating same includes, a substrate is provided and a P-well mid an N-well is formed in the substrate. The P-well and N-well have a well defined interface. A pre-determined area (pad window) crossing over the interface, is selected in the substrate. A first shallow trench isolation (STI) structure, a second STI structure, and a third STI structure are formed in the substrate within the pad window. The first STI structure is located over the interface, the second STI structure is located in the P-well and the third STI structure is located in the N-well. The second STI structure encloses a first inner region that is separated from a first outer region and the third STI structure encloses a second inner region that is separated from a second outer region. N-type doped regions are respectively formed in the first inner region of the P-well and in the second inner region of the N-well. First p-type doped regions are respectively formed in the first outer region of the P-well and in the second outer region of the N-well and second p-type doped regions are respectively formed in the first outer region of the P-well and in the second outer region of the N-well. The second p-type doped region of the P-well is formed under the n-type doped region to have an electrical contact with the n-type doped region in the P-well to form a zener diode. The second p-type doped region of the N-well is formed under the n-type doped region to have an electrical contact with the n-type doped region in the N-well to form another zener diode.
The n-type doped region of the N-well is electrically connected to power source VDD, the n-type doped region of the P-well and the p-type doped region of the N-well are electrically connected to the pad, and the p-type doped regions of P-well are electrically connected to ground Vss.
It is understood from the above embodiment that the invention protects a semiconductor internal circuitry from an ESD discharge through the ESD protection circuit device using zener diodes, located under the pad. Because the zener diodes are located under the pad, the ESD protection circuit device does not occupy extra surface area on the wafer thereby substantially increasing the integration of ICs.
It is to be understood that the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.